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« August 19, 2008 - September 18, 2008 »
 
08 / 19
(event)
Calibre Design-to-Silicon Platform Workshop - San Jose, CA
Start: 9:00 am

esign-to-silicon platform, a comprehensive suite of tools designed to address the complex handoff between design and manufacturing.
08 / 20
(event)
EDA Tech Forum - New Delhi, India
Start: 9:00 am
End: 5:00 pm

Traveling to over 15 cities worldwide, the EDA Tech Forum series is the largest EDA industry event, bringing together over 7,500 attendees every year from over 2,250 companies.
08 / 21
(event)
SystemVerilog Assertions and Functional Coverage - Morning Session: Cost: $199 - Sponsored by Aldec
Start: 8:00 am
End: 12:00 pm

Presenter: Ashok Mehta, DefineView Consulting

(event)
Aldec AVMS VI-06: Implementing a PCI Express 2.0 Solution
Start: 11:00 am
End: 12:00 pm

Presenter: Northwest Logic – Brian Daellenbach

(event)
SystemVerilog Assertions and Functional Coverage: Cost:$199 - Sponsored by Aldec
Start: 1:00 pm
End: 5:00 pm

Presenter: Ashok Mehta, DefineView Consulting
08 / 22
(event)
EDA Tech Forum - Bangalore, India
Start: 9:00 am
End: 5:00 pm

Traveling to over 15 cities worldwide, the EDA Tech Forum series is the largest EDA industry event, bringing together over 7,500 attendees every year from over 2,250 companies.
08 / 23
08 / 24
(event)
Hot Chips 20 - A Synposium on High Performance Chips - Stanford, CA
Start: 9:00 am
Start: Aug 24 2008 - 9:00am
End: Aug 26 2008 - 7:00pm

Agenda: 

08 / 25
(event)
Hot Chips 20 - A Synposium on High Performance Chips - Stanford, CA
(all day)
Start: Aug 24 2008 - 9:00am
End: Aug 26 2008 - 7:00pm

Agenda: 

08 / 26
(event)
Hot Chips 20 - A Synposium on High Performance Chips - Stanford, CA
End: 7:00 pm
Start: Aug 24 2008 - 9:00am
End: Aug 26 2008 - 7:00pm

Agenda: 

(event)
Innovation in Verification Seminar - San Jose
Start: 9:00 am
End: 3:00 pm

a day of Verification. Sessions covering
everything from CDC, Verification Management, Processor Based
08 / 27
(event)
EDA Tech Forum - Hsin-Chu, Taiwan
Start: 9:00 am
End: 5:00 pm

Traveling to over 15 cities worldwide, the EDA Tech
Forum series is the largest EDA industry event, bringing together over

(event)
RTL Reuse: Solving the Puzzle - Chicago, IL
Start: 9:00 am

Engineers reuse existing RTL to hit tighter schedules and reduce costs. Over 80% of ASIC and FPGA designs reuse RTL from a previous design.
08 / 28
(event)
RTL Reuse: Solving the Puzzle - Madison, WI
Start: 4:00 am

Engineers reuse existing RTL to hit tighter schedules and reduce costs. Over 80% of ASIC and FPGA designs reuse RTL from a previous design.
08 / 29
(event)
EDA Tech Forum - Seoul, Korea
Start: 9:00 am
08 / 30
08 / 31
09 / 1
09 / 2
09 / 3
09 / 4
(event)
EDA Tech Forum - Penang, Malaysia
Start: 9:00 am

Traveling to over 15 cities worldwide, the EDA Tech Forum series is the largest EDA industry event, bringing together over 7,500 attendees every year from over 2,250 companies.
09 / 5
(event)
Tutorial: Building Gigabit-rate Routers with the NetFPGA - Brno, Czech Republic
Start: 9:00 am
End: 5:30 pm

An open platform called the NetFPGA has been developed at Stanford University. The NetFPGA platform enables researchers and instructors to build high-speed, hardware-accelerated networking systems.
09 / 6
09 / 7
09 / 8
(event)
FPL 2008 - Heidelberg, Germany
Start: 8:00 am
Start: Sep 8 2008 - 8:00am
End: Sep 10 2008 - 1:15pm

The International Conference
on Field Programmable Logic and Applications (FPL) is the first and
largest conference covering the rapidly growing area of
09 / 9
(event)
FPL 2008 - Heidelberg, Germany
(all day)
Start: Sep 8 2008 - 8:00am
End: Sep 10 2008 - 1:15pm

The International Conference
on Field Programmable Logic and Applications (FPL) is the first and
largest conference covering the rapidly growing area of

(event)
FPGAworld'2008 - Lund
Start: 8:30 am
End: 4:00 pm

You are invited to attend the 5th annual FPGAworld Conference. This years conference will take place at Electrum Kista in Stockholm Sweden on September 11 and at Ideon Lund on September 9.

(event)
CDNLIVE! SILICON VALLEY - San Jose, CA
Start: 9:00 am
Start: Sep 9 2008 - 9:00am
End: Sep 11 2008 - 9:48am

CDNLive!
09 / 10
(event)
FPL 2008 - Heidelberg, Germany
End: 1:15 pm
Start: Sep 8 2008 - 8:00am
End: Sep 10 2008 - 1:15pm

The International Conference
on Field Programmable Logic and Applications (FPL) is the first and
largest conference covering the rapidly growing area of

(event)
CDNLIVE! SILICON VALLEY - San Jose, CA
(all day)
Start: Sep 9 2008 - 9:00am
End: Sep 11 2008 - 9:48am

CDNLive!
09 / 11
(event)
CDNLIVE! SILICON VALLEY - San Jose, CA
End: 9:48 am
Start: Sep 9 2008 - 9:00am
End: Sep 11 2008 - 9:48am

CDNLive!

(event)
FPGAworld'2008 - Stockholm
Start: 8:30 am
End: 7:00 pm

You are invited to attend the 5th annual
FPGAworld Conference. This years conference will take place at Electrum

(event)
Aldec Europe AVMS EI-01 - HW/SW Co-Verfication for Embedded Designs
Start: 3:00 pm
End: 4:00 pm

Presenter: Presenter: Aldec, Inc. Jaroslaw Kaczynski, Technical Marketing Engineer
09 / 12
(event)
IBC 2008 » Meet with the Xilinx Broadcast team at IBC 2008, stand 10.F30
Start: 3:00 am
Start: Sep 12 2008 - 3:00am
End: Sep 16 2008 - 3:59am

Our panel of broadcast experts will be there to discuss your current and future requirements and demonstrate our latest IP, reference designs and hardware for all areas of your system.
09 / 13
(event)
IBC 2008 » Meet with the Xilinx Broadcast team at IBC 2008, stand 10.F30
(all day)
Start: Sep 12 2008 - 3:00am
End: Sep 16 2008 - 3:59am

Our panel of broadcast experts will be there to discuss your current and future requirements and demonstrate our latest IP, reference designs and hardware for all areas of your system.
09 / 14
(event)
IBC 2008 » Meet with the Xilinx Broadcast team at IBC 2008, stand 10.F30
(all day)
Start: Sep 12 2008 - 3:00am
End: Sep 16 2008 - 3:59am

Our panel of broadcast experts will be there to discuss your current and future requirements and demonstrate our latest IP, reference designs and hardware for all areas of your system.
09 / 15
(event)
IBC 2008 » Meet with the Xilinx Broadcast team at IBC 2008, stand 10.F30
(all day)
Start: Sep 12 2008 - 3:00am
End: Sep 16 2008 - 3:59am

Our panel of broadcast experts will be there to discuss your current and future requirements and demonstrate our latest IP, reference designs and hardware for all areas of your system.

(event)
SystemVerilog Assertions and Functional Coverage; Methodology & Language Training Class Cost $1200 - Sponsored by Aldec
Start: 9:00 am

Presenter: Ashok Mehta, DefineView Consulting

(event)
DO-254 Compliance: Pitfalls and Solutions - Hartford, CT
Start: 9:30 am

DO-254 is a recent standard that affects PLD, FPGA and ASIC designs for in-flight HW systems.
09 / 16
(event)
IBC 2008 » Meet with the Xilinx Broadcast team at IBC 2008, stand 10.F30
End: 3:59 am
Start: Sep 12 2008 - 3:00am
End: Sep 16 2008 - 3:59am

Our panel of broadcast experts will be there to discuss your current and future requirements and demonstrate our latest IP, reference designs and hardware for all areas of your system.

(event)
Development of Software-Defined Radio Systems » Joint Seminar and exhibition with The MathWorks and Texas Instruments
Start: 9:00 am
End: 4:15 pm

This seminar will be of interest to any application, software and hardware engineers working on Software-Defined Radio Systems, Communication Systems or Signal Processing applications that may also us
09 / 17
(event)
Lattice® and Aldec®: Quick Timing Closure: Simulation and Debugging of Lattice Designs
Start: 11:00 am
End: 12:00 pm

Some designers skip timing simulation, not realizing that it can complement static timing analysis (STA) tools and help you achieve timing closure faster.
09 / 18
(event)
Accelerating Custom IC Layout with IC Station - San Jose, CA
Start: 9:30 am

In this technical hands-on workshop, you will use Mentor's layout editor, integrated routers, and verification solutions to take a design from schematic to DRC-correct layout in a fraction of the time

(event)
Aldec Europe AVMS EI-02 - Rapid ASIC emulation in FPGA with HES
Start: 3:00 pm
End: 4:00 pm

Presenter: Presenter: Aldec, Inc. Jaroslaw Kaczynski, Technical Marketing Engineer
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