Planet FPGA - All FPGA blogs at one place
Featured Articles
Power Implications of Implementing Logic Using FPGA Embedded Memory Blocks
September 10, 2008 - 4:03pm — scottcOn-chip user memory has become a common resource on modern FPGAs. This memory comes in the form of configurable Embedded Memory Blocks (EMB). EMBs are very area efficient for implementing designs
Take A Poll
FPGA newsgroup
FPGA News
- Weak Employment Data Contributes To Lower Close On Wall Street - Trading Markets (press release)
- Sports Diary - Fiji Times
- Symwave and PLDA Demonstrate Multi-Vendor USB 3.0 - Chip Design Magazine
- Guest bogger: Jim Hogan on IP - EDN.com
- Impulse C Tools Accelerate Xilinx FPGA HD Video - Chip Design Magazine
Events - Filter:
An open platform called the NetFPGA has been developed at Stanford University. The NetFPGA platform enables researchers and instructors to build high-speed, hardware-accelerated networking systems.
Presenter - Ashok Mehta, DefineView Consulting
An open platform called the NetFPGA has been developed at Stanford University. The NetFPGA platform enables researchers and instructors to build high-speed, hardware-accelerated networking systems.
Presenter: Doulos
This quarter, we're excited to host the exclusive presentation of David Whipp's "Stop Writing Assertions! Creating Efficient Verification Methodologies".
An open platform called the NetFPGA has been developed at Stanford University. The NetFPGA platform enables researchers and instructors to build high-speed, hardware-accelerated networking systems.
Presenter: Aldec
An open platform called the NetFPGA has been developed at Stanford University. The NetFPGA platform enables researchers and instructors to build high-speed, hardware-accelerated networking systems.
esign-to-silicon platform, a comprehensive suite of tools designed to address the complex handoff between design and manufacturing.
Traveling to over 15 cities worldwide, the EDA Tech Forum series is the largest EDA industry event, bringing together over 7,500 attendees every year from over 2,250 companies.
Presenter: Ashok Mehta, DefineView Consulting
Presenter: Northwest Logic – Brian Daellenbach
Presenter: Ashok Mehta, DefineView Consulting
Traveling to over 15 cities worldwide, the EDA Tech Forum series is the largest EDA industry event, bringing together over 7,500 attendees every year from over 2,250 companies.
Agenda:Â
Agenda:Â
Agenda:Â
a day of Verification. Sessions covering
everything from CDC, Verification Management, Processor Based
Traveling to over 15 cities worldwide, the EDA Tech
Forum series is the largest EDA industry event, bringing together over
Engineers reuse existing RTL to hit tighter schedules and reduce costs. Over 80% of ASIC and FPGA designs reuse RTL from a previous design.
Engineers reuse existing RTL to hit tighter schedules and reduce costs. Over 80% of ASIC and FPGA designs reuse RTL from a previous design.
Traveling to over 15 cities worldwide, the EDA Tech Forum series is the largest EDA industry event, bringing together over 7,500 attendees every year from over 2,250 companies.
An open platform called the NetFPGA has been developed at Stanford University. The NetFPGA platform enables researchers and instructors to build high-speed, hardware-accelerated networking systems.
FPGA Webcasts
Upcoming FPGA Events
- Incorporating SystemVerilog in a Productive FPGA Methodology Workshop - San jose, CA(Event or Conference)(4 days)
- Actel & Aldec: Innovative Reprogrammable Prototyping for Actel RTAX Space-Flight FPGA Designs(Event or Conference)(6 days)
- Europe Actel & Aldec: Innovative Reprogrammable Prototyping for Actel RTAX Space-Flight FPGA Designs(Event or Conference)(6 days)
- ASP-DAC 2009 - Yokohama, Japan(Event or Conference)(10 days)
Forums | IP Catalog | Development Board | Vendor Directory | Products | FPGA Conference | Events | Polls | FPGA News | FPGA Blogs | FPGA Jobs USA | FPGA Jobs Portal USA| FPGA Articles | PLD Types |Â Planet FPGA |Â FPGA Webcasts |Â FPGA Whitepapers
