Xilinx timing constraints

In order to ensure that no timing violation (like period, setup or hold violation) will occur in the working design, timing constraints must be specified.

The simplest way to set up constraints for Xilinx application is to use a GUI constraints editor, as described in on of the previous parts of the tutorial. The approach described below involves manual editing of the UCF file and is more powerful.

Basic timing constraints that should be defined include frequency (period) specification and setup/hold times for input and output pads. The first is done with the PERIOD constraint, the second - with the OFFSET constraint.

Specifying timing groups

Timing groups are sets of objects to which constraints should b? applied. There are some pre-defined groups, and more groups can be created by an FPGA designer.

There are many forms of timing constraints. Some of them will be discussed below, other can be found in Xilinx Constraints Guide.

One way to create a timing group is to link it with the particular net:

NET "net_name" TNM_NET = qualifier "tnm_name";

Here net_name is a name of clock net (signal), tnm_name is a name of the associated timing group, and qualifier is an optional condition which is used to include in the group only elements of particular types. Examples of qualifiers include FFS (for flip-flops), PADS (for pads), RAMS (for RAM modules).

TNM_NET example:
NET "CLK" TNM_NET = "clk_net";

This code defines a clk_net timing group associated with the CLK clock net and including all synchronous elements controlled by this net (since no qualifier has been specified).

Another way to define a timing group is to specify the name of the instance (module):

INST "inst_name" TNM = qualifier "tnm_name";

In this case all synchronous elements in inst_name (or those corresponding to qualifier when specified) are grouped in tnm_name group.

Specifying period

PERIOD constraint is used to define a clock period (or frequency) for the clock domain. Example:

NET "CLK" TNM_NET = "clk_net"; TIMESPEC "TS_clk_net" = PERIOD "clk_net" 10 ns;

This example defines a minimum period of 10 ns for CLK clock net (which corresponds to 100 MHz frequency). TS_clk_net is a constraint name, it can be any other.

Specifying offset

OFFSET constraint is used to specify external setup time for input pads or necessary hold time for output pads.

For input pads, OFFSET specifies a time before the (external) clock edge when the related data signals are set. Example:


For output pads, OFFSET specifies a minimum time after the clock edge when the related data signas can be deasserted. Example:


In this form, constraints are applied to all I/O pads related to CLK clock signal. There are also more specific timing constraints. For more information, see Xilinx Constraints Guide.

False paths

A false path is a path between two synchronous elements which formally exists, but by design won't be ever activated during the device operation. As such, false paths should be excluded from static timing analysis. It is done using the TIG constraint:

TIMESPEC "TSid" = FROM "from_grp" TO "to_grp" TIG;

Here TSid is an identifier of the constraint, and from_grp and to_grp are timing groups.

Multicycle paths

There are situatuions when a given combinational logic unit is designed to produce output after more than one clock cycles. Such paths must be defined as multicycle, otherwise implementation tools will try to fit them in one cycle, possible failing the place and route.

Example: imagine that we have a TS_clk_net TIMESPEC constraint for clock period. Then in order to define a multicycle path from the multi_start group to the multi_end group we should write:

TIMESPEC "TS_multicycle_01" = FROM "multi_start" TO "multi_end" TS_clk_net*2;

Facebook  Twitter  Linkedin  YouTube      RSS


Check out FPGA related videos

Find Us On Facebook