Synthesis and Implementation

Synthesis

Synthesis process transforms an HDL description to a schematic-like netlist. This task is performed by the synthesizer. We will use the XST synthesizer which is bundled with the ISE.

Select again Synthesis/implementation view in the combobox in the upper part of the sidebar.

To synthesize our module, select our top-level module and apply Synthesize-XST -> View Synthesis Report task to it. The synthesis should complete without errors or warnings.

Specifying constraints

Constraints are used to guide further implementation process. There are many types of constraints. For now, we will consider only two of them: timing constraints and I/O constraints.

In order to specify constraints, one first need to create an implementation constraints file (UCF). To do so, choose Create New Source task again.

The UCF file can be edited directly, but now we will use easier approach.

Timing Constraints

Timing constraints are needed to ensure that our device will work properly at specified frequency. The easiest way to enter a 50 MHz timing constraint is to run User Constraints -> Create Timing Constraints task, double-click on the CLK row and enter 50 MHz value as a period:

I/O Pad Assignment

To specify input/output pad numbers, we select User Constraints -> Assign Package Pins and enter the following data (these data were extracted from the board manual):

 

Signal	Pad	Levels	Drive	Slew rate
CLK	E12	LVCMOS33	Â	Â
LEDS<0>	R20	LVCMOS33	8	SLOW
LEDS<1>	T19	LVCMOS33	8	SLOW
LEDS<2>	U20	LVCMOS33	8	SLOW
LEDS<3>	U19	LVCMOS33	8	SLOW
LEDS<4>	V19	LVCMOS33	8	SLOW
LEDS<5>	V20	LVCMOS33	8	SLOW
LEDS<6>	Y22	LVCMOS33	8	SLOW
LEDS<7>	W21	LVCMOS33	8	SLOW

Implementation

Now we select Implement Design -> Place & Route -> Place & Route Report task. It will go automatically through all implementation stages (translate, map, place & route). The ISE will check timing also automatically.

The next step is to generate a bitstream file and to download it to our board using a download cable and iMPACT program. When everything is complete, we can see blinking LEDs on our board.

Xilinx design flow will be covered in more details in further chapters.

The FPGA tutorial has been created by 1-CORE Technologies, an FPGA design services provider.