In structural description, one module is described as a set of other modules connected to each other.
The modules are instantiated in the top-level module using special language constructs. For example, to instantiate the counter module from the previous example, one should write something like
counter_inst: component counter
Â port map( CLK => CLK, CLR => CLR, DOUT => counter_value );
Here counter is a name of the component and counter_inst is the name of the instance. One component can be instantiated many times with different instance names.
The names before arrows are formal parameters (names of the ports that should be the same as in entity declaration). The names after arrows are actual parameters (that is, signals in this module).
In order to be able to instantiate component in a top-level VHDL module, that components must be first declared. The declaration of component if similar to the declaration of entity:
component counter is
Â Port ( CLK : in STD_LOGIC; CLR : in STD_LOGIC; DOUT : out STD_LOGIC_VECTOR (7 downto 0));
end component counter;
The component declaration should be located in the architecture block before the begin keyword.
In Verilog there is no need in component declaration, and component instantiation is done as follows:
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