Simulation

To check the correctness of our code we must write a testbench that drives our inputs (CLK input in this example). Then we should run a simulator and analyze resulting waveforms.

To create a testbench, we choose Add New Source, select VHDL TestBench module type and select a main module to be associated with the testbench. ISE will generate most part of it.


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY main_test_vhd IS
END main_test_vhd;

ARCHITECTURE behavior OF main_test_vhd IS

 COMPONENT main
 PORT(
  CLK : IN std_logic;
  LEDS : OUT std_logic_vector(7 downto 0)
  );
 END COMPONENT;

 SIGNAL CLK : std_logic := '0';
 SIGNAL LEDS : std_logic_vector(7 downto 0);

BEGIN

 uut: main PORT MAP(
  CLK => CLK,
  LEDS => LEDS
 );

 process is
 begin
  CLK<='1';
  wait for 10 ns;
  CLK<='0';
  wait for 10 ns;
 end process;
END;

In order for testbench file to be visible, choose "Behavioral Simulation" in the combobox in the upper part of the sidebar.

Now we select Xilinx ISE Simulator -> Simulate Behavioral Model task. It works, but we don't see our LEDS output changing, because it should change once per a second, which is a very big time for simulation. Thus, we have to decrease counter_max value in main.vhd. Let's set it to 16 (X”00000010”), for example. Now we can see LEDS value changing:

Note that verification method involving manual analysis of the waveforms can be used only for very simple designs. For more complex designs one should use automatic test environments that not only drive input signals, but also automatically compare results.

Don't forget to change the counter_max value back to X"2FAF07F".

The FPGA tutorial has been created by 1-CORE Technologies, an FPGA design services provider.

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