RTL design

The basic level for FPGA design entry is Register Transfer Level which represents a digital circuit as a set of connected primitives (adders, counter, multiplexers, registers etc.)

There are two basic ways to create an RTL design: schematic entry and HDL entry. Schematic entry is somewhat close to netlist: it is not very convenient to use it for large projects. HDL entry is more convenient, but needs an additional program (synthesizer) in order to translate HDL description to netlist.

The FPGA tutorial has been created by 1-CORE Technologies, an FPGA design services provider.

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