Ports and signals declarations
To declare a module, input and output ports must be declared. For instance, consider a 8-bit counter. VHDL description of this counter starts with the entity declaration:
entity counter is
Â Port ( CLK : in STD_LOGIC;
Â CLR : in STD_LOGIC;
Â DOUT : out STD_LOGIC_VECTOR (7 downto 0)
STD_LOGIC and STD_LOGIC_VECTOR are basic data types used in VHDL, defined in IEEE standard 1164. STD_LOGIC can represent the following values: 1, 0, U (undefined), X (unknown), Z (high impedance), W (weak), H (weak 1), L (weak 0), - (don't care). STD_LOGIC_VECTOR is an array of STD_LOGIC.
The similar description in Verilog will look like:
module counter(clk, clr, dout);
Â input clk;
Â input clr;
Â output [7:0] dout;
Signal is a basic element in HDL languages, similar to a variable in programming languages (actually, VHDL supports not only signals, but also the so-called "variables", but the latter are rarely used for purposes other than simulation). Signals must be declared explicitly.
Example of a signal declaration in VHDL:
signal value: std_logic_vector(7 downto 0);
In VHDL signals are declared in the architecture block before the begin keyword.
Unlike VHDL, Verilog uses two types of signals: signals of the first type ("wire") can be outputs of concurrent statements, while signals of the second one ("reg") can be outputs of sequential statements (i.e. registers). Example of a signal declaration in Verilog:
wire [7:0] combinational_value;
reg [7:0] register_value;
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