History of the programmable logic

Discrete logic ICs

Prior to the invention of programmable logic electronic systems designers had to use specialized integrated circuits, each of which contained just a few gates. Such chips were called discrete logic. In order to create even a moderately complex device one had to mount a few tens of chips on one board. This led to more complex board layout and reduced performance.

Programmable Logic Arrays (PLAs)

The first kind of programmable logic device (named Programmable Logic Array – PLA) was introduced in early 70's. PLAs were one-time programmable chips containing AND and OR gates and able to implement a simple logic function represented as a disjunctive normal form. A PLA device can be defined by a three parameters:

  1. number of inputs,
  2. number of AND gates (terms),
  3. number of OR gates (= number of outputs).

A simplified diagram of the PLA device with 4 inputs, 4 terms and 3 outputs is shown below:

Note that logic gates are fixed, only the commutation matrices are programmable. The commutation matrix is based on fuses that are programmed by burning.

For further information on how to implement an arbitrary logic function with a combination of AND and OR gates, refer to the literature on disjunctive normal form.

There was also a variation of this architecture in which only the first commutation matrix (before AND gates) was programmable, and the second one was hardwired. These devices were called Programmable Array Logic.

Complex Programmable Logic Devices (CPLDs)

Complex Programmable Logic Devices (CPLDs) can be seen as a continuation of the PLA architecture. The CPLD chip includes logic blocks (macrocells) at the borders of the chip, and a connection matrix located at the central part.

Each macrocell has a structure similar to PLA. So, a CPLD device can be also seen as a set of PLAs on one chip with programmable interconnects.

CPLDs are usually Flash-based, that is, the configuration of macrocells and the interconnection matrix is defined by contents of the on-chip Flash memory. It means that CPLD need not to be configured after each power-up, unlike the SRAM-based FPGAs.

It must be noted that there are also Flash-based FPGAs. The main difference between CPLD and FPGA is not in configuration memory, but in the underlying architecture.

The FPGA tutorial has been created by 1-CORE Technologies, an FPGA design services provider.

1-CORE Technologies logo

Facebook  Twitter  Linkedin  YouTube      RSS


Check out FPGA related videos

Find Us On Facebook