Hardware description languages (HDL)

The hardware description languages are used to formally define how the device should operate. This is a more portable and convenient alternative to creating a circuit from elements.

Actually, the HDLs were initially designed to assist simulation rather than replace schematic design entry. Synthesizers (programs that translates HDL description to a gate-level netlist) were created later. Therefore HDL languages have two subsets of language constructs: synthesizable (suitable for synthesis and simulation) and non-synthesizable (suitable only for simulation).

The two major HDL languages are VHDL and Verilog. Both of these languages are widespread. VHDL is more Pascal-like (or, to be more precise, Ada-like) and Verilog is more similar to C. VHDL is a strong-typed language, and Verilog is more weak-typed.

The syntax constructs of HDL languages are similar to those of conventional programming languages. However, the semantics is quite different.

Note that in VHDL identifiers are case-insensitive, and in Verilog they are case-sensitive.

• Ports and signals declarations
• Assignments and processes
• Structural description

The FPGA tutorial has been created by 1-CORE Technologies, an FPGA design services provider.