FPGA synthesis and implementation (Xilinx design flow)

This chapter describes FPGA synthesis and implementation stages typical for Xilinx design flow.

Synthesis

The synthesizer converts HDL (VHDL/Verilog) code into a gate-level netlist (represented in the terms of the UNISIM component library, a Xilinx library containing basic primitives). By default Xilinx ISE uses built-in synthesizer XST (Xilinx Synthesis Technology). Other synthesizers can also be used.

Synthesis report contains many useful information. There is a maximum frequency estimate in the "timing summary" chapter. One should also pay attention to warnings since they can indicate hidden problems.

After a successful synthesis one can run "View RTL Schematic" task (RTL stands for register transfer level) to view a gate-level schematic produced by a synthesizer.

XST output is stored in NGC format. Many third-party synthesizers (like Synplicity Synplify) use an industry-standard EDIF format to store netlist.

Implementation

Implementation stage is intended to translate netlist into the placed and routed FPGA design.

Xilinx design flow has three implementation stages: translate, map and place and route. (These steps are specific for Xilinx: for example, Altera combines translate and map into one step executed by quartus_map.)

Translate

Translate is performed by the NGDBUILD program.

During the translate phase an NGC netlist (or EDIF netlist, depending on what synthesizer was used) is converted to an NGD netlist. The difference between them is in that NGC netlist is based on the UNISIM component library, designed for behavioral simulation, and NGD netlist is based on the SIMPRIM library. The netlist produced by the NGDBUILD program containts some approximate information about switching delays.

Map

Mapping is performed by the MAP program.

During the map phase the SIMPRIM primitives from an NGD netlist are mapped on specific device resources: LUTs, flip-flops, BRAMs and other. The output of the MAP program is stored in the NCD format. In contains precise information about switching delays, but no information about propagation delays (since the layout hasn't been processed yet.

For Virtex-5 devices MAP also does placement (see below). For other devices placement is done by PAR. Routing is done by PAR for all devices.

Place and route

Placement and routing is performed by the PAR program.

Place and route is the most important and time consuming step of the implementation. It defines how device resources are located and interconnected inside an FPGA.

Placement is even more important than routing, because bad placement would make good routing impossible. In order to provide possibility for FPGA designers to tweak placement, PAR has a "starting cost table" option.

PAR accounts for timing constraints set up by the FPGA designer. If at least one constraint can't be met, PAR returns an error.

The output of the PAR program is also stored in the NCD format.

For Virtex-5 devices, placement is performed by MAP instead of PAR.

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