Design Entry

Let's add a source file to our project. To do this, choose Create New Source task and select VHDL module source type. We will name our module main.

Our first design will make the on-board LEDs to blink sequentially, one at a time. The board has 8 LEDs, so we have to specify 8-bit output bus (one signal to control each LED) and one input signal (a clock source).

Now we need to describe our design in VHDL. It will contain two small parts:

  • a cyclic shift register with '1' in one bit and '0' in the other ones – to turn on one LED at a time;
  • as our input clock frequency is 50 MHz (from an on-board oscillator), we need to make a counter to shift data in our register roughly 1 time per second.

The following code implements this behavior:


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity main is
 Port(
  CLK : in STD_LOGIC;
  LEDS : out STD_LOGIC_VECTOR (7 downto 0)
 );
end main;

architecture Behavioral of main is
signal leds_control_register: std_logic_vector(7 downto 0):="00000001";
signal counter: std_logic_vector(31 downto 0):=X"00000000";
constant counter_max: std_logic_vector(31 downto 0):=X"2FAF07F";
begin

process (CLK) is
begin
if rising_edge(CLK) then
  if counter<counter_max then
   counter<=counter+1;
  else
   counter<=X"00000000";
  end if;
 end if;
end process;

process (CLK) is
begin
 if rising_edge(CLK) then
  if counter=X"00000000" then
   leds_control_register<=leds_control_register(6 downto 0)&leds_control_register(7);
  end if;
 end if;
end process;

LEDS<=leds_control_register;

end Behavioral;

The FPGA tutorial has been created by 1-CORE Technologies, an FPGA design services provider.

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