Creating a simple FPGA project

FPGA design process involves the same sequence of actions for every FPGA design software suite:

  • Create a project (choose a name, an FPGA device, a default language etc.)
  • Add files to project (both HDL descriptions of the target device and testbenches for behavioral simulation).
  • Behavoiral simulation.
  • Synthesis (an automatic process to translate HDL description to a netlist).
  • Implementation and bitstream generation.

Now we will proceed with the specific example of a simple FPGA project directed to Xilinx Spartan-3A FPGA using the Spartan-3A Starter Kit (a starter kit isn't needed to create a project and to produce a bitstream, but it is needed to ensure that the design works in hardware). The steps for other vendors' FPGAs are basically the same.

We will use a free downloadable Xilinx ISE WebPack both as simulation and implementation tool.

Creating a project

At first, we must to create a project. It is done by using File->New Project menu item. A dialog will appear asking to select project name and folder. Choose Next to setup basic project parameters.

To create a design for Spartan-3A Starter Kit we must choose xc3s700a in FG484 package as out target device. We will also use VHDL as our preferred language.

The next dialogs offer us to create and/or add files to the project. We'll skip them at this time.

Now, the project is created. The ISE main window includes a sidebar, which is placed on the left side by default. The upper part of the sidebar displays a tree listing all project files, and the lower part lists tasks that are applicable for the file that is selected in the upper part.

The FPGA tutorial has been created by 1-CORE Technologies, an FPGA design services provider.

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