The basics of digital circuit design

Combinational and Sequential Circuits

Combinational circuit is a circuit containing no memory units (such as latches and flip-flops). There output is completely defined by the current input states (the previous input states don't matter). Every combinational circuit produces a delay, that is, its outputs settle in some time after input signals has been asserted.

Sequential circuit is a therefore a circuit containing memory units. A register (block of flip-flops or latches) is an essential part of a typical sequential circuit. In a sequential circuit registers are controlled by a clock signal. The set of registers controlled by one clock signal is called a clock domain. Complex circuits can have multiple clock domains.

Complex logic designs can be split into combinational logic sub-circuits communicating via registers.

Timing requirements

The following rules apply to synchronous circuits:

  1. Setup time (Ts). All register inputs must be constant during this time before a corresponding clock edge.
  2. Hold time (Th). All register inputs must be constant during this time after a corresponding clock edge.

There are two other effects that must be taken into account when elaborating sequential circuits:

  • Clock skew is an effect of non-simultaneous clock switching at the inputs of different registers (controlled by one clock signal).
  • Clock jitter is an effect of phase noise in a clock signal.

Thus a maximum propagation delay of a combinational circuit must satisfy the following condition:

Tpmax <= Tclk - Ts - δt,

where Tclk is a clock period, Ts is a setup time and δt accounts for skew and jitter.

The FPGA tutorial has been created by 1-CORE Technologies, an FPGA design services provider.

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