Assignments and processes

Concurrent assignments

Concurrent assignment is used to make a signal equal to some expression. Concurrent assignment works always, i.e. it is not an one-time operation, but a permanent binding. Example of concurrent assignment in VHDL:

c <= a and b;

The same statement in Verilog:

assign c = a & b;

Concurrent assignments can be conditional. For example, in the following VHDL code c is assigned a value of a if sw is '1', and a value of b otherwise:

c <= a when sw='1' else b;

The same operation in Verilog:

assign c = sw ? a : b;


A process in VHDL or Verilog is a mean to take complex actions when some signals change. Flip-flops and latches are typically described as processes. But a process can define something more complex than a simple flip-flop or latch.

process (CLK,CLR) is
 if CLR='1' then
 elsif rising_edge(CLK) then
 end if;
end process;

The signals in brackets after process keyword make up a sensitivity list. A process can be thought as executing each time when one of the signals in the sensitivity list. This affects only behavioral simulation: synthesizers ignore sensitivity lists.

The same process in Verilog:

always @ (posedge CLK or posedge CLR) begin
 if (CLR) val<=0;
 else val<=val+1;

Sequential assignments

Sequential assignments are those assignments that are located inside processes. Sequential assignments can be nonblocking or blocking.

Nonblocking sequential assignment operator changes the signal value only after the completion of the process. For instance, the following code:

process (CLK) is
 if rising_edge(CLK) then
 end if;
end process;

will leave val2=val (and not val+1) after execution.

Nonblocking sequential assignment operators are the most basic (operators in the above examples are also nonblocking) and provides more or less predictable synthesis results.

Blocking sequential assignment operators change the signal value immediately, more like a conventional programming language.

To use blocking assignment in VHDL, one needs to declare a variable instead of a signal and to use ":=" operator instead of "<=".

To use blocking assignment in Verilog, one needs to simply use "=" operator instead of "<=".

Note that synthesis results for blocking assignment are often unpredictable, their use in synthesizable code can be considered bad design practice unless absolutely needed.

The FPGA tutorial has been created by 1-CORE Technologies, an FPGA design services provider.

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