Xilinx Spartan-6 LX16 Evaluation Kit

The Avnet Spartan-6 LX16 Evaluation Kit is an excellent low-power reference platform.  The Xilinx Spartan-6 FPGA introduces significant enhancements in the low-power FPGA arena, with indu

TopJTAG Probe 1.7.0 Released

A new 1.7.0 version of TopJTAG Probe -- a low-cost circuit visualization and debugging software employing boundary-scan (IEEE 1149.1 JTAG) technology -- is now available.

TopJTAG Probe screenshot

System Test and Validation Engineer opening at Silicon Image in Sunnyvale, CA

Local Candidates Preferred. 2+ Yrs. of experience in designing tools for Automatic Chip Validation.

Dynamic Partial Reconfigurability of FPGA's

Now a days FPGA’s have become the number one choice for any Hardware Developer when it comes to ASIC design or Future proof design. Over the last 12 years FPGA’s have grown to mind boggling proportions in the number of gates per FPGA and the variety of ip-blocks avialble . They have in fact overlapped some the functionality of an ASIC/ASSP and in some areas surpassed their performance.

One the most outstanding features of FPGA’s that have given them the edge over ASIC/ASSP is their full cum partial dynamic reconfigurability.

FPGA design tutorial

A new FPGA design tutorial is being written. It focuses primarily on Xilinx design flow, but the supplied information should be applicable for any FPGA architecture.

JTAGTest now with "logic analyzer" functionality

New version of SECONS JTAGTest, JTAG IEEE 1149.1 debugging and programming solution, now supports signal recording and offline viewing.

This means that JTAGTest can use your JTAG connection to IEEE 1149.1 compliant device (such as FPGA, CPLD, or microprocessor) as a quite powerful logic analyzer. Look at the following picture which shows measured signal on a Xilinx XC95xx design:

JTAGTest logic analyzer

Power Implications of Implementing Logic Using FPGA Embedded Memory Blocks

On-chip user memory has become a common resource on modern FPGAs.This memory comes in the form of configurable Embedded Memory Blocks (EMB).  EMBs are very area efficient for implementing designs that require storage; However, for logic-intensive designs that do not require storage, the chip area devoted to EMBs become wasted. This need not be the case if the EMBs are configured as Read-Only-Memories (ROMs) and used to implement logic. Recall that a ROM is essentially a large Look-Up-Table (LUT), and LUTs are the traditional resource used to implement logic on an FPGA.

JTAGTest: JTAG IEEE 1149.1 Debugging and Testing Solution

SECONS has launched JTAGTest, IEEE 1149.1 debugging and testing tool. Main features include:

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FPGA Central Jobs portal is a great way to reach all the FPGA Genius who visit the site. The jobs posted here are also visible across the web like LinkedIn, MySpace, OpenSemi Jobs and many more.  We currently display 5000+ FPGA & CPLD related jobs from around the web.

FPGA Central usually charges $39 for a posting, but for a Limited Time we will offer these for FREE. We want the employers to see how effective the medium could be.

To post the FREE job visit - then "Post a Job" or directly visit . When asked use the discount code "HIREFPGA" (All caps no quotes). Send us an email at "info at fpgacentral dot com" if you have queries.

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