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Altera Demonstrates Industry's Highest Performance DDR4 Memory Data Rates ... - Businessweek

December 23, 2014 - 6:45am

Altera Demonstrates Industry's Highest Performance DDR4 Memory Data Rates ...
Businessweek
18, 2014 /PRNewswire/ -- Altera Corporation (Nasdaq: ALTR) today announced it is demonstrating in silicon DDR4 memory interfaces operating at an industry-leading 2,666 Mbps. Altera's Arria™ 10 FPGAs and SoCs are the industry's only FPGAs available ...

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Altera Quartus II Software v14.1 Enables TFLOPS Performance in Industry's First ... - Businessweek

December 23, 2014 - 6:45am

Businessweek
Altera Quartus II Software v14.1 Enables TFLOPS Performance in Industry's First ...
Businessweek
15, 2014 /PRNewswire/ -- Altera Corporation (Nasdaq: ALTR) today released its Quartus™ II software v14.1 featuring expanded support for Arria™ 10 FPGAs and SoCs, the FPGA industry's only devices with hardened floating point DSP blocks and the ...

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FPGA/RTL Engineer - The Beacon

December 20, 2014 - 1:08am

FPGA/RTL Engineer
The Beacon
At CompuCom, we set you up for job success right from the start. Our precision recruiting process aligns the right fit for the right people. We are looking for an experienced FPGA/RTL Engineer to work for one of the worlds top 500 fortune companies. Skills and ...

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Stay on: Altera Corp. (NASDAQ:ALTR), Navistar International Corporation ... - Property Mentor

December 19, 2014 - 7:04am

Stay on: Altera Corp. (NASDAQ:ALTR), Navistar International Corporation ...
Property Mentor
Altera Corporation (NASDAQ:ALTR) has released its Quartus II software v14.1 featuring expanded support for Arria 10 FPGAs and SoCs, the FPGA industry's only devices with hardened floating point DSP blocks and 20 nm SoC FPGAs that integrate ARM ...

Maxim, Linear, Xilinx hit with BofA downgrades - Seeking Alpha

December 19, 2014 - 6:30am

Maxim, Linear, Xilinx hit with BofA downgrades
Seeking Alpha
BofA/Merrill has respectively downgraded analog/mixed-signal chipmakers Maxim (NASDAQ:MXIM) and Linear (NASDAQ:LLTC) to Underperform and Neutral, and FPGA vendor Xilinx (NASDAQ:XLNX) to Underperform. In addition, Goldman has cut Maxim to ...

Microsemi's SmartFusion2 SoC FPGAs and IGLOO2 FPGAs Security Technology ... - IT Business Net

December 19, 2014 - 2:05am

Microsemi's SmartFusion2 SoC FPGAs and IGLOO2 FPGAs Security Technology ...
IT Business Net
ALISO VIEJO, Calif., Dec. 18, 2014 /PRNewswire/ --Microsemi Corporation (Nasdaq: MSCC), a leading provider of semiconductor solutions differentiated by power, security, reliability and performance, today announced its SmartFusion2 SoC FPGAs and ...

Industry's Highest Performance DDR4 Memory Data Rates in an FPGA - CTIMES

December 18, 2014 - 10:45pm

CTIMES
Industry's Highest Performance DDR4 Memory Data Rates in an FPGA
CTIMES
Altera Corporation announced it is demonstrating in silicon DDR4 memory interfaces operating at an industry-leading 2,666 Mbps. Altera's Arria 10 FPGAs and SoCs are the industry's only FPGAs available today that support DDR4 memory at these data rates, ...

Popular Bitcoin Mining Software - Investopedia

December 18, 2014 - 8:10am

Popular Bitcoin Mining Software
Investopedia
While the hardware used by miners is broadly of three types: CPU/GPU (Graphical Processing Units), FPGA (Field Programmable Gate Array) and ASIC (Application Specific Integrated Circuits), the choice for the software is broader. Here's a list of some of the ...

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Digital ASIC Design Engineers - ASIC, GPU - ElectronicsWeekly.com

December 18, 2014 - 7:27am

Digital ASIC Design Engineers - ASIC, GPU
ElectronicsWeekly.com
Are you ready to work within one of the world's fastest growing and most exciting technology companies……? We are seeking a number of skilled Digital ASIC Design Engineers with solid ASIC / RTL / FPGA design skills and a passion for graphics technology, ...

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Algorithmic Library Function Developer - ElectronicsWeekly.com

December 17, 2014 - 4:18am

Algorithmic Library Function Developer
ElectronicsWeekly.com
An exciting opportunity is now available to join my client as a DSP Algorithms Engineer ( Algorithms / FPGA ). Working within a small team that is a part of a much larger global company, you will be contributing to providing market-leading programmable ...

PLDA ultra-compact System-on-Module Enables Lighthouse Imaging to Speed ... - Broadway World

December 16, 2014 - 9:45am

PLDA ultra-compact System-on-Module Enables Lighthouse Imaging to Speed ...
Broadway World
Featuring an ARM dual-core Cortex-A9 MPCore and up to 350K of advanced low-power FPGA logic cells, the SoMZ platform combines the flexibility and ease of programming of a CPU with the configurability and parallel processing power of an FPGA.

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Verification IP supports PCIe 4.0. - ThomasNet News (press release) (blog)

December 16, 2014 - 6:08am

Verification IP supports PCIe 4.0.
ThomasNet News (press release) (blog)
December 16, 2014 - With design-aware Mentor® EZ-VIP PCI Express Verification IP, engineers can reduce time spent building test benches for ASIC and FPGA design verification. PCIe EZ-VIP includes pre-packaged verification environments for serial and ...

Altera Quartus II Software v14.1 enables TFLOP performance - Automated Trader

December 16, 2014 - 3:50am

Altera Quartus II Software v14.1 enables TFLOP performance
Automated Trader
San Jose, Calif - Altera Corporation has released its Quartus II software v14.1 featuring expanded support for Arria 10 FPGAs and SoCs, the FPGA industry's only devices with hardened floating point DSP blocks and 20 nm SoC FPGAs that integrate ARM ...

and more »

Altera software accelerates Arria 10 FPGAs - ElectronicsWeekly.com

December 16, 2014 - 1:37am

ElectronicsWeekly.com
Altera software accelerates Arria 10 FPGAs
ElectronicsWeekly.com
These include OpenCL for software programmers, DSP Builder for model-based designers and hardware description language (HDL) flows for traditional FPGA designers. Unlike a soft implementation, hardened floating point DSP blocks do not consume ...

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FPGA wakes processor on voice command - ElectronicsWeekly.com

December 16, 2014 - 12:42am

FPGA wakes processor on voice command
ElectronicsWeekly.com
The idea is that the main application processor stays asleep while the always-on FPGA listens for valid speech – waking the main processor when it has verified the speech. Either IP block will fit in a 2.1×2.1mm FPGA (36 ball, 0.35mm pitch). “Accurate and ...

Digital/FPGA Engineer - circa 45K - Essex - ElectronicsWeekly.com

December 15, 2014 - 1:25pm

Digital/FPGA Engineer - circa 45K - Essex
ElectronicsWeekly.com
My client is a leading, global engineering company. Their range of products are used across a vast range of industries. A requirement has been signed off within the R&D Department in their Essex site for a Senior FPGA Engineer. The successful candidate ...

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Unlocking the Secrets of ASIC Clock Conversion - Design and Reuse (press release) (blog)

December 15, 2014 - 10:22am

Unlocking the Secrets of ASIC Clock Conversion
Design and Reuse (press release) (blog)
I read an online article this week which flagged an issue with FPGA-based prototyping, clock conversion. Clock conversion is one of the most important aspects to successful prototyping and this week's blog is dedicated to sharing information enabling you to ...

Senior Digital Design Engineer - FPGA, High Speed Digital - ElectronicsWeekly.com

December 15, 2014 - 7:32am

Senior Digital Design Engineer - FPGA, High Speed Digital
ElectronicsWeekly.com
Based in Cambridge, the Senior Digital Design Engineer will b joining a small consultancy with a focus in High Speed Video, Multimedia and network intelligence. Responsibilities will be include High Speed Digital Board Design FPGA Design, and will focus ...

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FPGAs 'essential' to electronics design engineers - New Electronics

December 15, 2014 - 2:42am

FPGAs 'essential' to electronics design engineers
New Electronics
FPGAs are becoming an increasingly important tool in the electronics designer's armoury. But while the devices are being applied in a wide range of markets, there is a suspicion that FPGA skills across UK industry may not be matched to the application ...

Ultra low-latency 10Gbit/s Ethernet 10GBASE-R PHY/PCS - Design and Reuse (press release)

December 14, 2014 - 6:34am

Ultra low-latency 10Gbit/s Ethernet 10GBASE-R PHY/PCS
Design and Reuse (press release)
Ultra-low latency is achieved by using only the PMA function in FPGA Multi-Gigabit transceivers and moving all PCS functions to code that is optimized for 10GBASE-R. This allows the data to take the shortest, and hence the lowest latency, path to and from ...

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