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What timing! my first post on FPGA’s & Xilinx/Digilent/Avnet announce a Arduino compatible entry level FPGA!

Digilent now also have it @ $99 & avail from 15th Oct. It’s the same board as Avnet’s, as the logos of both Digilent & Avnet are on the board.

XiLinx, have now updated their product page for the Arty, with documentation & a short video on their blog.

Xilinx says the kit includes –

• Full seat Vivado® Design Suite: Design Edition
  • Node locked & Device-locked to the Artix-7 XC7A35T FPGA, with 1 year of updates and support

The catch is that after one year of  free updates, updates may be a bit pricey, not the cost of the initial purchase ($3k!), but expect a few $$’s. Of course if the S/W is stable, there may be no need to upgrade for a few years or so, if at all.

I’m not sure how many FPFA’s have Arduino headers but one from HackaDay, may have been a predecessor, as it was mentioned in XiLinx’s blog.

Papilio also have an open-source hardware and software project, FPGA board with Arduino headers, that can use a customised Arduino IDE. And then “It lets you draw up circuits without investing time and energy in learning VHDL/Verilog”.

And then there is the Mojo V3, it doesn’t seem to have directly compatable Arduino headers but does use an Arduino IDE to include Arduino libraries in their projects.

Of course FPGA’s have the ability to “Software Define” any processor, if it can fit into the FPGA. Presumable the Arty already has the avrmega 8-bit series mcu defined with plenty of support.

Digilent have good VHDL or Verilog tutorials extracted from one of their textbooks, that now would be a good time to work through & just see if I can really make sense of these gizzmo’s! And if so then maybe place an order for the Arty!

Well, it’s almost inevitable to cross path’s with FPGA’s (Field Programmable Gate Arrays) when playing around with micro-controllers, embedded systems & digital electronics. To me they’ve been a black box and  a bit of a mystery, even though they have been around for a while.

After reading FPGA’s For Dummies, followed by the DE0 Nano User Manual, they started to make a bit more sense. Throw in a VHDL Tutorial  and this FPGA intro,  and I’m getting the general idea.

The FPGA devices are dominated by XiLinx & Altera, who provide Hardware Development Environments with a choice of HDL’s (Hardware Design Languages) – VHLD or Verilog. Companies like Digilent also offer a range of development boards.

FPGA’s main advantage are their parallel computing capabilities, and for that reason they are worth knowing about even for hobbyists. However the development boards are more expensive compared to mcro-controllers & SBC’s like BeagleBone’s etc.  And they are considerably more complex &  offer a whole new range of challenges.

There are many applications that use FPGA devices, even the Analog Discovery uses a XiLinx FPGA. They can be used in Bitcoin mining, Big Data applications & Video processing. High End development boards cost $10k+, whereas entry level dev boards start from approx $100.

An understanding of Digital Logic is essential & the more the better. I’ve brushed up a bit with Basic Digital Electronics to give well a basic understanding of Digital Electronics, it certainly helps but I think I need to do more to be able to tackle FPGA’s. I’m getting there & hope to try one out shortly, as they offer a whole new field of exploration or maybe more realistically a world of “bleeding-edge” pain!

With no specific project in mind, except maybe setting up a Led Matrix array, I’m not sure what I would do with one, other than to work through various tutorials & projects I can find on the net. I’ll keep an eye out for any projects that may be of use & post it here of course!

Interesting … I just noticed that Digilent is now offering (as yet unavailable! & price unknown) a new dev board Arty Artix-7 with Arduino headers. It seems comparable to the Basys3, minus a few of the buttons, leds & 7 segment displays & also most importantly – no $10 Vivado Design Edition (big loss!). Instead it’s supplied with the free Web Edition development environment, which may be enough.

Nevertheless it should be a good entry level FPGA, especially after working thru the Make:AVR Programming book. I expect it too be a bit cheaper than the Basys3, but maybe not by much. It should provide a lot more interest as a stepping stone to using a FPGA. Although I don’t think this is the first FPGA dev board to include Arduino headers.

Well there you go… hot of the press…Avnet Introduces New “ARTY” Xilinx Artix-7 35T FPGA Evaluation Kit   & Product Brief from Avnet, interestingly it includes a Xilinx Vivado: Design Edition, device locked licence. And at a price @ $99 v $149 for the Basys3.

You have an FPGA circuit and you want the user to interact with your circuit by pushing a button. Clearly, you need a button, right? Not so fast! [Clifford Wolf] recently found a mysterious effect that lets him detect when someone pushes on his iCEstick board.

The video below shows the mystery circuit (which is just the stock iCEstick board), which appears to react any time you flex the PC board. The Verilog implements a simple ring oscillator (basically an inverter with its output tied to its input).

Here’s an excerpt from his Verilog code:

// ring oscillator wire [99:0] buffers_in, buffers_out; assign buffers_in = {buffers_out[98:0], chain_in}; assign chain_out = buffers_out[99]; assign chain_in = resetn ? !chain_out : 0; SB_LUT4 #( .LUT_INIT(16'd2) ) buffers [99:0] ( .O(buffers_out), .I0(buffers_in), .I1(1'b0), .I2(1'b0), .I3(1'b0) );

He compares the output frequency to a known frequency from the onboard crystal oscillator and registers large shifts as a push. At first we thought it might be mechanical flex on the crystal, but if you watch the video, the output of the ring oscillator is clearly shifting on a touch. Presumably (and this is a guess), small changes in the capacitance and other circuit parameters have an effect on the ring oscillator’s frequency. [Clifford] says he has many theories, but doesn’t know which one (if any) is correct.

We can’t decide if we’d depend on this effect or not in practice. But it does seem repeatable in the video. Maybe [Clifford] has invented a new product category: the Field Programmable Gate Array and Switch (FPGAS). We’ve mentioned [Clifford’s] work before on project iCEstorm and even used his open source tool chain in our FPGA tutorial (look for another one soon, by the way).

Thanks for the tip [James Bowman].

"This FPGA Project was completed on Christmas Day 2013. I wanted to assemble surface mount components, and to do this I need a reflow oven. Everybody on the internet seems to build their own, so I set about building one using a FPGA. Everything has been implemented inside the FPGA, without there being any software in the control loop."

One of the challenges with display technology is the huge increase in bandwidth that has occurred since LCD panels took over from Cathode Ray Tubes. Low end laptops have a million pixels, UHD (“4K”) displays
have 8 million and the latest Full Ultra HD (“8k”) displays have over 33 million pixels. Updating all those pixels takes a lot of bandwidth – to update a 4k display at 60 Hz refresh rates takes close to a gigabyte per second. 8 billion bits – that is a lot of bits! That’s why VGA ports and even DVI ports are starting to vanish in favor of standards like HDMI and DisplayPort.

The current release of HDMI is 2.0, and is tightly licensed with NDAs and licensing fees. VESA, who created the DisplayPort standard, states the standard is royalty-free to implement, but since January 2010, all new DisplayPort related standards issued by VESA are no longer available to non-members.

So after receiving a new Digilent Nexys Video FPGA development board, Hackaday regular [Hamster] purchased a UHD monitor, scoured the internet for an old DisplayPort 1.1 standard, and started hacking.

A couple of months and 10,000 lines of VHDL code later what may be the first working Open Source DisplayPort
implementation is available. The design includes a 16-bit scrambler, an 8b/10b encoder, and multichannel support.

We had noticed that [Eli Billauer] had done something similar, but as far as we know his source is unreleased (although he has some interesting notes about what he found). Although [Hamster] is the first to admit that it is not yet production ready, this forms a base for the others who will no doubt follow. Nothing makes life easier than a reference implementation to compare against!

The video below is a talk about DisplayPort 1.3 from [CraigWiley] who is on the VESA standards committee and includes a good overview of the technical details at a high level. If you are looking for other Displayport hacks, you can drive an external display from an iPad or even drive a Retina display from any Displayport output.

[DisplayPort Plug Image by Belkin CC-BY-SA]

DECA, a new Altera MAX10 FPGA evaluation board from Arrow/Terasic, is the most versatile low cost FPGA board I have.
I’m planning to write a series covering some projects for DECA, and the graphics is the first topic.
I’m using Quartus 15.0 for Linux Update 2 for the projects.

Here’s some details about the DECA.

Currently it sells for $169. Arrow holds a series of global workshops covering DECA since May 2015.
The small form factor FPGA board packs with features:

• High end MAX10 device with 50,000 LEs, and pin count 22×22
• 4 PLLs
• Dual ADCs
• 512MB DDR3
• 64MB Flash
• 10/100 Ethernet
• USB2.0 OTG
• SDHC
• HDMI v1.4 Transmitter
• MIPI CSI-2
• 24bit Audio
• 2 SMA inputs
  Various sensors
  • Gesture, Proximity/Ambient light
  • Humidity and temperature
  • Power monitor
  • Accelerometer
• BeagleBone I/O expansion headers

The board I have is an evaluation kit comes with a wireless WiFi/BLE BeagleBone Cape and a 8M camera module. In my opinion, BeagleBone I/O expansion makes many kinds of interesting DIY projects possible.

The graphics for MAX10 is implemented in VIP (Altera Video and Image Processing Suite IPs).
The following block diagram shows the FPGA setup and software processes for graphics rendering.

There are some challenges, the tough hardware and software ones are listed below:

• Choosing proper parameters for VIP components to generate proper video timing signals
• Low graphics rendering frame rate. In 1024×768 resolution, HMI application’s rendering performance is in the range of couple frames per second.

Hardware Challenges

To address the video timing issue (i.e., pixels drawn to the screen are not properly displayed), different parameters are tried to configure IP cores. This design uses DDR3 controller with 64 bit Avalon interface data width. The Frame Reader IP (VFR), which converts user graphics/image/video data stored in external memory to a video stream understood by VIP, should have the same master port data width as the DDR3 controller. According to the VIP user guide, VFR’s control register “Frame Words” should be “The number of words (reads from the master port) to read from memory for the frame”.

To calculate the “Frame Words”, VFR pixel counts is used as the dividend and 2 (64/32) as the divisor. This configuration worked for one resolution, but not in other resolutions. Different VFR’s master port widths were tried (32 and 128), but had the same result. After days of struggles, I finally settled down the proper parameter combination working with all 640×480, 800×480 and 1024×768 resolutions.

IP Parameter Value DDR3 Controller Avalon Interface Data Width 64 Frame Reader Master Port Width 256 Color Plane Sequencer Halve Control Packet Width disabled

Other key things I learned from hardware perspective:

• With the current configuration, it can only have up to two VFRs in the design, or Quartus Analysis & Synthesis, namely quarts_map, will crash. I believe the reason is the hardware resource limitation from the parts used in DECA
• To get correct DDR3 pin assignments and interconnects, run deca_vip_mem_if_ddr3_emif_p0_pin_assignments.tcl at least once, after Analysis & Synthesis but before Fitter (Place & Route) compilation. The reminding notice is buried in synthesis compiling messages.

Software Challenges

The graphics software demonstration is done in uCOS II environment, it has 3 tasks. The main task performs HMI (Human-Machine Interface) displaying 640×480 automotive glass cluster.

The other rendering task draws two vertical and horizontal bars in 800×480 screen. The third task moves the main HMI screen.
When the HMI screen is in 1024×768 resolution, the rendering frame rate is in the range of 1 to 2 fps. If the resolution is reduced to 640×480, fps improves but is still slow. Further investigation indicates the performance issue lies within HMI code itself, not necessary due to VIP or graphics implementation.
HMI code used is based on Altia’s proprietary framework.
In theory, the graphics hardware has enough bandwidth to drive a 640×480 32bit/pixel screen approaching 30 fps.
The following NIOS II Eclipse screenshot shows assembly and C code snippet of a pixel filling routine.

The Nios II Gen 2 softcore is clocked by a 100MHz PLL. Assuming in a best scenario, there is no CPU pipeline stall, no RTOS context switch, and one clock cycle per instruction.
The inner loop (j loop) takes:
2 + ( 2 + ( 5 + 6 ) * inner_loop_count ) cycles.
The outer loop (i loop) takes:
( 2 + ( inner_loop_cycles + 7 + 6 ) * outer_loop_count ) cycles
Therefore to update 640×480 pixels screen, cycle total needed is 3,388,320, or it takes about 33ms or in 30 fps. This is a simplified case, the actual frame rate depends on rendering content and will be of course much lower.
VFR supports two frame buffers, and the feature is very useful for double buffering. While displaying the front buffer, you can build scene in the back buffer and swap the buffers when the back buffer building is done. Although it won’t improve rendering performance, the technique effectively eliminates video flickering. The demo code for the drawing task uses the approach.

The hardware design, software demo code and HMI library, plus prebuilt FPGA bitstream and application binary are available at:
https://github.com/fpga4fun/deca_graphics
Note: I don’t have commercial VIP license, the prebuilt bitstream is time-limited.
You may need turn off and then on the HDMI monitor for the monitor to pick up the video signal (at least for the Sceptre monitor I’m using).

This video clip shows the complete process to configure FPGA, download and run graphics demo from command line, and debug the code from Eclipse for Nios.

When you think of a CNC controller you probably think of a PC with a parallel port or some microcontroller-based solution like a Smoothie Board. [Mhouse1] has a different idea: use FPGAs as CNC controllers.

FPGAs inherently handle things in parallel, so processing G code, computing curves and accelerations, and driving multiple stepper motors at one time would not be an issue at all for an FPGA. Most computer-based designs will have slight delays when trying to drive everything at once and this introduces some mechanical jitter. Even worse jitter occurs when you have an old PC trying to run everything when some other task takes over the CPU.

In all fairness, [Mhouse1’s] design does  include an Altera CPU on the FPGA to handle some tasks that CPUs are good at, but the FPGA allows the design to create I/O devices specifically for the task at hand. The CPU is also running an RTOS (MicroC OS II) and a Python GUI that runs on a controlling PC.

There’s an older article about using an FPGA to control a CNC machine that has a lot of good information about designing such a beast, if you are interested. However, that design is a lot less ambitious than this one. [Mhouse1] wants the controller to be machine agnostic, and he’s demonstrated it on a cheap DVD-based laser cutter as well as a modified Shapeoko machine.

If you want an introduction to FPGAs, you might want to get started with our tutorial on cheap FPGA development. Or, you can learn a lot with just your Web browser.

A while back I had a poke at porting the J1 FORTH softcore to Altera.

Yep, ahead of my meanderings with the Altera LABS but I have spent years in software development and real-time DSP and other systems so the LABS are just me being methodical and giving back to the community.  My main aim, eventually, is DSP and vision experiments.

Not being a slouch I then speed off to at least play at a larger level of granularity and so the FORTH softcores.

Any old how, J1 did allude me because it is coded for XILINX and had some pesky RAM code definition that did not come with the J1.  Ended up finding the XILINX code for the RAM and so I have got most of the way through the porting.  Just some pesky problems with Altera version of Verilog not covering the same expanse of the spec as the XILINX compiler.

All good, as it is all a learning vehicle.

Stay tuned then.

Stocks simply were looking for direction on Monday after gains on Friday. The Dow is still down 10% from highs and investors keep proving that they are willing to buy pullbacks. 24/7 Wall St. reviews dozens of analyst research reports each morning to find new trading and investing ideas for its readers. Some analyst calls cover stocks to buy, while others cover stocks to sell or avoid.

These are this Monday’s top analyst upgrades, downgrades and initiations.

AeroVironment Inc. (NASDAQ: AVAV) was raised to Overweight from Neutral with a $28.00 price target (versus a $20.44 prior close) at Piper Jaffray. AeroVironment has a consensus analyst price target of $29.00 and a 52-week trading range of $20.13 to $31.94.

Gold Fields Inc. (NYSE: GFI) was downgraded to Underweight from Neutral at JPMorgan. The stock closed at $2.75 and has a consensus analyst price target of around $4.00 and a 52-week trading range of $2.35 to $6.01.

Marvell Technology Group Ltd. (NASDAQ: MRVL) was downgraded to Equal Weight from Overweight with a lower price target of $9.50 (versus an $8.84 close, after a 16% price drop) at Morgan Stanley. The firm B. Riley also downgraded Marvell to Neutral from Buy with a $10.00 price target. This is after several other downgrades were issued by firms after the company’s disclosure of investigations into accounting irregularities.

Nokia Corp. (NYSE: NOK) was already rated as Buy at Goldman Sachs, but the firm added Nokia to its prized Conviction Buy List. Nokia closed at $6.51 and was indicated up around $6.53 after the call. The Finnish tech giant has a 52-week range of $5.71 to $8.73 and a consensus price target of $8.97.

Silver Wheaton Corp. (NYSE: SLW) was downgraded to Market Perform from Outperform at BMO Capital Markets. Silver Wheaton closed at $11.62, has a consensus price target of $21.71 and has a 52-week range of $11.03 to $24.22. Its 52-week low was just hit last Friday.

5 Oil and Gas Stocks Analysts Want You to Buy Now

Other key analyst upgrades, downgrades and initiations on Monday were seen as follows:

Alexion Pharmaceuticals Inc. (NASDAQ: ALXN) was downgraded to Equal Weight from Overweight with a $205.00 price target (versus a $171.93 close) at Barclays.

AstraZenec PLC (NYSE: AZN) was raised to Buy from Hold at Deutsche Bank.

BHP Billiton PLC (NYSE: BHP) was raised to Buy from Hold at Jefferies.

BioMed Realty Trust Inc. (NYSE: BMR) was raised to Overweight from Sector Weight at KeyBanc Capital Markets.

Cynosure Inc. (NASDAQ: CYNO) was raised to Buy from Hold with a $44.00 price target (versus a $33.80 close) at Stifel Nicolaus.

Exelon Corp. (NYSE: EXC) was raised to Buy from Neutral with a $33.00 price target (versus a $29.70 close) at SunTrust Robinson Humphrey.

Goldcorp Inc. (NYSE: GG) was maintained as Sector Perform and the price target was cut to $18.00 from $19.00 (versus a $12.63 close) at RBC Capital Markets.

H&R Block Inc. (NYSE: HRB) was downgraded to Neutral from Buy at BTIG, based mostly on valuation after a very big pop.

ALSO READ: Will You Buy a $949 iPhone 6s?

Mattress Firm Holding Corp. (NASDAQ: MFRM) was downgraded to Neutral from Buy with a $55.00 price objective (versus a $46.24 close) at Bank of America Merrill Lynch.

ONEOK Inc. (NYSE: OKE) was started as Neutral at Credit Suisse, although its $41.00 price target implies handy upside to the $35.19 closing price as Credit Suisse’s ratings coverage is relative to peers.

Randgold Resources Ltd. (NASDAQ: GOLD) was downgraded to Neutral from Overweight with an $87.00 price target (versus a $57.84 close) at JPMorgan.

Sierra Wireless Inc. (NASDAQ: SWIR) was reiterated as Buy and with a $38.00 price target (versus a $21.87 close) at Canaccord Genuity. The call is based on enterprise solutions product execution being expected to deliver sustainable long-term growth.

Spirit Realty Capital Inc. (NYSE: SRC) was downgraded to Neutral from Buy with an $11.00 price target (versus a $9.27 close) at Merrill Lynch.

Taubman Centers Inc. (NYSE: TCO) was raised to Overweight from Sector Weight at KeyBanc Capital Markets.

Vertex Pharmaceuticals Inc. (NASDAQ: VRTX) was raised to Overweight from Equal Weight with a $150.00 price target at Barclays.

Woodward Inc. (NASDAQ: WWD) was started as Market Perform with a $48.00 price target (versus a $44.26 close) at Cowen.

Xilinx Inc. (NASDAQ: XLNX) was raised to Buy from Neutral with a $50.00 price target (versus a $41.93 close) at Goldman Sachs.

ALSO READ: 4 Top Growth Stock Picks From Jefferies

In case you missed Friday’s top analyst upgrades and downgrades, they included BP, Chevron, Lululemon Athletica, Petrobras, Motorola Solutions, Shake Shack, Under Armour and over a dozen more companies.

You have an old PC with a nonstandard RGB video out and you need to bring it to a modern PAL TV set. That’s the problem [svofski] had, so he decided to use an Altera-based DE1 board to do the conversion. Normally, you’d expect reading an RGB video signal would take an analog to digital converter, which is not typically present on an FPGA. Instead of adding an external device, [svofski] used a trick to hijack the FPGA’s LVDS receivers and use them as comparators.

The scheme does take a few discrete components to level shift the input signal and to provide an RC integrator. The integrator is used as a digital to analog converter, allowing the FPGA to compare the incoming signal with an output voltage. Once the analog signal is digitized, it is relatively straightforward to convert it to any format you want. Going back to the analog domain is as simple as a pulse width or pulse density modulation scheme and an RC filter (or you could use a simple R2R DAC).

The result is a very low parts count project that gets the job done. Of course, this is a complete hack of the LVDS I/O in the FPGA. If you want to hear more about the real use of LVDS, see the video below.

SeeedStudio Logic Start Shield VHDL FPGA Development On The Papilio DIY Maker Open Source BOOOLE Of

“The amount of design wins and early adoptions are ahead of wherewe expected them to be,” says Gavrielov. “We’re definitely ahead of plan in terms of yield,” adds Gavrielov,”we’re not seeing yield issues on HPL. It’s a high k metal gateprocess but it’s a less complex process than the HP process – ithas less mask steps.” He attributes the high yields to the “very intimate” linkage inprocess development with TSMC and to the decision Xilinx made to use TSMC’s HPL processrather than the LP and HP processes chosen by companies which havestruggled. He adds that there are aspects of the HP process wh

Xeltek aims to provide high quality and performance products at a reasonable cost. Xeltek China has been set up and in operation since 1992. It has been growing steadily over the years expanding in engineering, manufacturing, sales, and support. As a result, we are proud to provide high performance products at very reasonable cost to customers in the world market today.

Xeltek SuperPro 5000/5004GP currently supports 58K+ devices and 60K device support maybe already passed while you are reading this article. This is a true milestone and a new standard of the industry unmatched by any other company.

As of third week of Feb. 2010, Superpro5000/5004GP device support reached 58,149. This is the largest number in the industry today. So, what does this number mean and how is Xeltek able to support such a large number of devices?

Download #free #eBook FPGAs For Dummies

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• The pros and cons of using FPGAs
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Working with Lattice FPGAs recently, I had a need to program one but couldn’t find my ‘proper’ (Chinese clone, bought from eBay) programming adapter. When I started the Diamond Programmer software, though, it claimed it could see a USB programming adapter. It turned out that I’d left an FTDI ‘FT2232H Mini Module‘ attached to the PC. I use the module for all sorts of little debugging exercises: most often as a dual serial port for serial port debugging, but it also works for programming Parallax Propeller microcontrollers.

As luck would have it, the Diamond software recognises the unadulterated FT2232H as a legitimate USB programmer, and pressing the ‘Detect Cable’ button finds it. Note that if you plug in a new USB device, the Diamond Programmer software needs restarting before it can see it.

The FT2232H has two ports, A and B, and these appear as ports FTUSB-0 and FTUSB-1 in the Diamond software. All that remained was to figure out the wiring. Fortunately, there are a lot of clues in the schematics of various Lattice evaluation boards, particularly the MachXO2 Pico Board and the iCE40 Ultra Breakout Board.

Here’s the wiring, both for SPI and JTAG, referred to the pins on the Mini Module. I chose to use port B since it was more convenient for my prototype board. Translating the wiring to port A is left as an exercise for the reader.

SPI JTAG FT2232H Mini Module SO TDI DBUS1 CN3-25 SI TDO DBUS2 CN3-24 SCK TCK DBUS0 CN3-26 SS_B ISPEN DBUS4 CN3-21 CRESET TRST DBUS7 CN3-18 GND GND GND CN3-2,4

It works well, and does exactly what it should.

FPGA Market – Global Industry Analysis, Size, Share, Growth, Trends and Forecast, 2014 – 2020 Industry Analysis, Size, Share, Growth, Trends and Forecast, 2012 – 2018  

Report Description

This market research study analyzes the FPGA system market on a global level, and provides estimates in terms of revenue (USD million) from 2014 to 2020. It recognizes the drivers and restraints affecting the industry and analyzes their impact over the forecast period. Moreover, it identifies the significant opportunities for market growth in the next few years.

A field-programmable gate array (FPGA) is an integrated circuit or semiconductor device used to implement logical function that an application-specific integrated circuit (ASIC) could perform, but the ability to update the functionality after manufacturing offers advantages such as re-programming in the field for rapid prototyping and debugging for many applications. FPGAs use programmable routing channels and pre-built logic blocks for implementing custom hardware functionality depending upon the embedded system developer configuring these devices. FPGAs are programmed and configured using Hardware Description Language (HDL) such as VHDL and Verilog. Some key benefits of FPGA technology are high performance, shorter time to market, cost effective solutions, reliability and long term maintenance.

Complete Report with TOC @ http://www.mrrse.com/field-programmable-gate-array-market .

Scope

The global FPGA market is segmented by region into North America, Europe, Asia Pacific (APAC) and Rest of the World (RoW). Geographically, Asia Pacific led the global FPGA market share in 2013. Countries such as Japan, China, India, Taiwan, and South Korea are key markets for consumer electronics, industrial, and automotive applications. Japan contributed to huge market share of the global FPGA market in 2013. FPGA market is highly concentrated among the players such as Xilinx Inc, Altera Corporation, Lattice Semiconductors and other regional and local companies, which have substantial presence across the U.S. and Canada, Europe and Asia Pacific.

This report provides strategic analysis of the global FPGA market, and the growth forecast for the period 2014 to 2020. The span of the report includes competitive analysis of various market segments based on the types, module and in-depth cross sectional analysis of the FPGA market across different geographic segments. To support strategic decision making, the report also includes profiling of leading players in the industry, their market share and various strategies adopted by them. The Porter’s Five Forces analysis and market attractiveness analysis included in the report provide insight into market dynamics and industry competition.

Key Players

The report also provides company market share analysis of the various industry participants with company overview, financial overview, business strategies, SWOT analysis, and recent developments in the field of FPGA market. Major market participants profiled in this report include Xilinx Inc., Altera Corporation, Lattice Semiconductor Corporation, Microsemi Corporation, among others.

Request a Sample Copy of the Report @ http://www.mrrse.com/sample/297 .

About MRRSE

MRRSE stands for Market Research Reports Search Engine, the largest online catalog of latest market research reports based on industries, companies, and countries. MRRSE sources thousands of industry reports, market statistics, and company profiles from trusted entities and makes them available at a click. Besides well-known private publishers, the reports featured on MRRSE typically come from national statistics agencies, investment agencies, leading media houses, trade unions, governments, and embassies.

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Three months ago Intel said it would buy chip maker Altera in a deal valued at $16.7 billion. It was a significant investment for the world’s largest chip company and much was made over the consolidation in the semiconductor industry. On Thursday however, we got a lot more color on why Intel plans to plunk down a considerable hunk of money for Altera.

It basically boils down to this one statistic offered up by Jason Waxman, the VP & GM of the cloud platforms group at Intel. Waxman said that by 2020 Intel believes a third of the data center market could be using the type of chips that Altera specializes in.

Altera makes a type of chip called a field programmable gate array, or FPGA, that’s really a fancy way of saying a type of chip that can be reprogrammed after its made. The industry has traditionally used FPGAs in specialty scenarios as opposed to putting them in common servers or workstations because they are larger, cost more, and generally don’t perform as efficiently as general purpose chips.

In presentations covering the data center, where clients like Microsoft are using FPGAs to run their search algorithms to presentations on accelerators where future machine-learning customers are eyeing FPGAs to run neural networks, Intel sees FPGAs everywhere. In the networking word, FPGAs are already present in cellular base stations, and Intel [fortune-stock symbol=”INTC”] is hoping to gain more market share inside those boxes with, yes, its FPGAs.

Basically, Intel sees FPGAs like I see Sriracha. They belong everywhere.

Intel’s optimism isn’t totally unfounded; it’s part of a shift to agility and customization that’s playing out at all levels of the hardware ecosystem. As “software eats the world,” it’s tougher to be a chip company designing and building a product that requires 18 months to go from idea to something physical. At least with an FPGA, you can offer a physical product that can be changed, even if that ability to tweak it comes at a cost.

There’s an opportunity here too for startups trying to alter the current FPGA model to make it a little bit more flexible. For example, the startup Flex Logic is trying to make an FPGA that is a little bit faster than the current generation of chips. On the software side, BitFusion hopes to help companies run their code on the most optimal hardware for their current job without having to rewrite that code for the chip underneath—be it an FPGA or not.

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For more on Intel, check out the following Fortune video:

[fortune-brightcove videoid=4293286829001]

Getting into FPGA design isn’t a monolithic experience. You have to figure out a toolchain, learn how to think in hardware during the design, and translate that into working Verliog. The end goal is getting your work onto an actual piece of hardware, and that’s what this post is all about.

In the previous pair of installments in this series, you built a simple Verilog demonstration consisting of an adder and a few flip flop-based circuits. The simulations work, so now it is time to put the design into a real FPGA and see if it works in the real world. The FPGA board we’ll use is the Lattice iCEstick, an inexpensive ($22) board that fits into a USB socket.

Like most vendors, Lattice lets you download free tools that will work with the iCEstick. I had planned to use them. I didn’t. If you don’t want to hear me rant about the tools, feel free to skip down to the next heading.

Hiccups with Lattice’s Toolchain

Still here? I’m not one of these guys that hates to sign up for accounts. So signing up for a Lattice account didn’t bother me the way it does some people. What did bother me is that I never got the e-mail confirmation and was unable to get to a screen to ask it to resend it. Strike one.

I had tried on the weekend and a few days later I got a note from Lattice saying they knew I’d tried to sign up and they had a problem so I’d have to sign up again. I did, and it worked like I expected. Not convenient, but I know everyone has problems from time to time. If only that were the end of the story.

I was impressed that Lattice does support Linux. I downloaded what appeared to be a tgz file. I say appeared because tar would not touch it. I examined the file and it looked like it was gzipped, so I managed to unzip it to a bare file with a tar extension. There was one problem: the file wasn’t a tar file, it was an executable. Strike two. I made it executable (yes, I’m daring) and I ran it. Sure enough, the Lattice installer came up.

Of course, the installer wants a license key, and that’s another trip to the Web site to share your network card’s MAC address with them. At least it did send me the key back fairly quickly. The install went without incident. Good sign, right?

I went to fire up the new software. It can’t find my network card. A little Internet searching revealed the software will only look for the eth0 card. I don’t have an eth0 card, but I do have an eth3 card. Not good enough. I really hated to redo my udev rules to force an eth0 into the system, so instead I created a fake network card, gave it a MAC and had to go get another license. Strike 3.

I decided to keep soldiering (as opposed to soldering) on. The tool itself wasn’t too bad, although it is really just a simple workflow wrapper around some other tools. I loaded their example Verilog and tried to download it. Oh. The software doesn’t download to the FPGA. That’s another piece of software you have to get from their web site. Does it support Linux? Yes, but it is packaged in an RPM file. Strike 4. Granted, I can manually unpack an RPM or use alien to get a deb file that might work. Of course, that’s assuming it was really an RPM file. Instead, I decided to stop and do what I should have done to start with: use the iCEStorm open source tools.

TL;DR: It was so hard to download, install, and license the tool under Linux that I gave up.

Programming an FPGA Step-by-Step

Whatever tools you use, the workflow for any FPGA is basically the same, although details of the specific tools may vary. Sometimes the names vary a bit, too. Although you write code in Verilog, the FPGA has different blocks (not all vendors call them blocks) that have certain functions and methods they can connect. Not all blocks have to be the same either. For example, some FPGAs have blocks that are essentially look up tables. Suppose you have a look up table with one bit of output and 16 rows. That table could generate any combinatorial logic with 4 inputs and one output. Other blocks on the same FPGA might be set up to be used as memory, DSP calculations, or even clock generation.

Some FPGAs use cells based on multiplexers instead of look up tables, and most combine some combinatorial logic with a configurable flip flop of some kind. The good news is that unless you are trying to squeeze every bit of performance out of an FPGA, you probably don’t care about any of this. You write Verilog and the tools create a bitstream that you download into the FPGA or a configuration device (more on that in a minute).

The general steps to any FPGA development (assuming you’ve already written the Verilog) are:

• Synthesize – convert Verilog into a simplified logic circuit
• Map – Identify parts of the synthesized design and map them to the blocks inside the FPGA
• Place – Allocate specific blocks inside the FPGA for the design
• Route – Make the connections between blocks required to form the circuits
• Configure – Send the bitstream to either the FPGA or a configuration device

The place and route step is usually done as one step, because it is like autorouting a PC board. The router may have to move things around to get an efficient routing. Advanced FPGA designers may give hints to the different tools, but for most simple projects, the tools do fine.

Constraints For Hardware Connected to Specific Pins (or: How does it know where the LED is?)

There is one other important point about placing. Did you wonder how the Verilog ports like LED1 would get mapped to the right pins on the FPGA? The place and route step can do that, but it requires you to constrain it. Depending on your tools, there may be many kinds of constraints possible, but the one we are interested in is a way to force the place and route step to put an I/O pin in a certain place. Without that constraint it will randomly assign the I/O, and that won’t work for a ready made PCB like the iCEStick.

For the tools we’ll use, you put your constraints in a PCF file. I made a PCF file that defines all the useful pins on the iCEstick (not many, as many of you noted in earlier comments) and it is available on Github. Until recently, the tools would throw an error if you had something in the PCF file that did not appear in your Verilog. I asked for a change, and got it, but I haven’t updated the PCF file yet. So for now, everything is commented out except the lines you use.

Here’s a few lines from the constraint file:

set_io LED3 97  # red set_io LED4 96  # red set_io LED5 95  # green

Every external pin (including the clock) you plan to use must be defined in the constraint file. Errors in the file can be bad too. Routing an output to a pin that is connected, for example, directly to ground could damage the FPGA, so be careful! The picture to the right shows the configuration with my PCF file (the center LED and the one closest to the FPGA chip just blink and are not marked in the picture). Keep in mind, though, you could reroute signals any way that suited you. That is, just because LED1 in the Verilog is mapped to D1 on the board, doesn’t mean you couldn’t change your mind and route it to one of the pins on the PMOD connector instead. The name wouldn’t change, just the pin number in the PCF file.

Configuring an FPGA

Different FPGAs use different technology bases and that may affect how you program them. But it all starts with a bitstream (just a fancy name for a binary configuration file). For example, some devices have what amounts to nonvolatile memory and you program the chip like you might program an Arduino. Usually, the devices are reprogrammable, but sometimes they aren’t. Besides being simpler, devices with their own memory usually start up faster.

However, many FPGAs use a RAM-like memory structure. That means on each power cycle, something has to load the bitstream into the FPGA. This takes a little time. During development it is common to just load the FPGA directly using, for example, JTAG. However, for deployment a microprocessor or a serial EEPROM may feed the device (the FPGA usually has a special provision for reading the EEPROM).

The FPGA on the iCEstick is a bit odd. It is RAM-based. That means its look up tables and interconnections are lost when you power down. The chip can read an SPI configuration EEPROM or it can be an SPI slave. However, the chip also has a Non Volatile Configuration Memory (NVCM) inside. This serves the same purpose as an external EEPROM but it is only programmable once. Unless you want to dedicate your iCEstick to a single well-tested program, you don’t want to use the NVCM.

The USB interface on the board allows you to program the configuration memory on the iCEstick, so, again, you don’t really care about these details unless you plan to try to build the device into something. But it is still good to understand the workflow: Verilog ? bitstream ? configuration EEPROM ? FPGA.

IceStorm

Since I was frustrated with the official tools, I downloaded the IceStorm tools and the related software. In particular, the tools you need are:

• Yosys – Synthesizes Verilog
• Arachne-pnr – Place and Route
• Icestorm – Several tools to actually work with bitstreams, including downloading to the board; also provides the database Arachne-pnr needs to understand the chip

You should follow the instructions on the IceStorm page to install things. I found some of the tools in my repositories, but they were not new enough, so save time and just do the steps to build the latest copies.

There are four command lines you’ll need to program your design into the iCEstick. I’m assuming you have the file demo.v and you’ve changed the simulation-only numbers back to the proper numbers (we talked about this last time). The arachne-pnr tool generates an ASCII bitstream so there’s an extra step to convert it to a binary bitstream. Here are the four steps:

• Synthesis: yosys -p "synth_ice40 -blif demo.blif" demo.v
• Place and route: arachne-pnr -d 1k -p icestick.pcf demo.blif -o demo.txt
• Convert to binary: icepack demo.txt demo.bin
• Configure on-board EEPROM: iceprog demo.bin

Simple, right? You do need the icestick.pcf constraint file. All of the files, including the constraint file, the demo.v file, and a script that automates these four steps are on Github. To use the script just enter:

./build.sh demo

This will do all the same steps using demo.v, demo.txt, and so on.

Try It Out

Once the board programs, it will immediately start operating. Remember, this isn’t a program. Once the circuitry is configured it will start doing what you meant it to do (if you are lucky, of course). In the picture below (and the video), you can see my board going through the paces. I have some buttons for the two adder inputs on one side and a reset button on the other. I also soldered some headers to the edge of the board.

If you are lazy, you can just use a switch or a jumper wire to connect the input pins to 3.3V or ground. It looks like the device pins will normally be low if you don’t connect anything to them (but I wouldn’t count on that in a real project). However, I did notice that without a resistor to pull them down (or a switch that positively connected to ground) there was a bit of delay as the pin’s voltage drooped. So in the picture, you’ll see I put the switches to +3.3V and some pull down resistors to ground. The value shouldn’t be critical and I just grabbed some 680 ohm resistors from a nearby breadboard, but that’s way overkill. A 10K would have been smarter and even higher would probably work.

If it works, congratulations! You’ve configured an FPGA using Verilog. There’s still a lot of details to learn, and certainly this is one of the simplest designs ever. However, sometimes just taking that first step into a new technology is the hardest and you’ve already got that behind you.

Although you can do just about anything with an FPGA, it isn’t always the best choice for a given project. Development tends to be harder than microcontroller development (duplicating this project on an Arduino would be trivial, for example). Also, most FPGAs are pretty power hungry (although the one we used is quite low power compared to some). Where FPGAs excel is when you need lots of parallel logic executing at once instead of the serial processing inherent in a CPU.

FPGAs get used a lot in digital signal processing and other number crunching (like Bitcoin mining) because being able to do many tasks all at once is attractive in those applications. Of course, it is possible to build an entire CPU out of an FPGA, and I personally enjoy exploring unusual CPU architectures with FPGAs.

Then again, just because you can make a radio with an IC doesn’t mean there isn’t some entertainment and educational value to building a radio with transistors, tubes, or even a galena crystal. So if you want to make your next robot use an FPGA instead of a CPU, don’t let me talk you out of it.

I’ve just been doing some work with the iCE40 series of FPGAs from Lattice Semiconductor. They’re small FPGAs, with up to 7680 gates, and they’re very low-power, which is nice for mobile applications. From what I can gather, Lattice acquired the designs when they bought a company called SiliconBlue in 2011. I’ve been used to using the Lattice Diamond software with their other chips, but the iCE40 chips aren’t supported by Diamond. Instead, they get their own software called iCEcube2. It’s a bit of a pain to use and not very well documented. I’ve just been through the process of starting a project and getting a very basic design working, and I’m writing about it here in case someone else finds it useful.

The iCEcube2 software looks convincingly like an IDE, but it isn’t, really. It doesn’t even seem to have a way of creating new source code files, and the order in which some things have to be done is not at all obvious. I think iCEcube2 is really designed for taking existing designs and implementing them on the Lattice iCE40 chips. While the software is a complete dog’s breakfast, it does have the key advantage of being free. You do need to create a node-locked licence for it using their licencing page.

To start an empty project, double click Project -> New Project. Select the chip you’re going to use. This creates a folder with the title of the project, containing:

• <project>_sbt.project
• <project>_syn.prj
• folder <project>_Implmnt, containing folder sbt, containing folders constraint, log and outputs. All are empty apart from iceCube0.log in log folder.

Now you can add your source files. If you click on ‘Synthesis Tool’, then an ‘Add Synthesis Files’ menu item appears, but clicking on this doesn’t do anything useful. You have to right-click on ‘Add Synthesis Files’ and select ‘Add Files…’ from the pop-up menu. Go figure. I used a very simple VHDL source file:

LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY test IS PORT ( d: in std_logic; q: out std_logic; qn: out std_logic; ); END test; ARCHITECTURE rtl OF test IS BEGIN q <= d; qn <= not d; END rtl;

At this point I’d expect to be able to allocate signal names (d, q and qn, in this case) to pins on the device package. But you can’t do that yet in the wonderful world of iCEcube2. All the buttons on the toolbar are greyed out. The way to proceed is to double click ‘Run Synplify Pro Synthesis’. Hopefully your code will compile without errors, and lots of files get created.

The project folder now contains:

• stdout.log and stdout.log.bak
• synlog.tcl
• loads of stuff under <project>_Implmnt

Two new files appear in the project under ‘P&R Flow’: <project>.edf and <project>.scf.

Now double-click ‘Run P&R’. The design will get placed and routed, and a bitmap gets generated for programming the chip.

At this point the toolbar buttons for timing constraints, pin constraints, floor planner, package view, power estimator and timing analysis become active. Hurrah! Now you can change your pin constraints.

Click on ‘Pin Constraints Editor’, the fourth icon from the left. Put in the pin locations for the signals you want. Make sure you click the ‘locked’ checkboxes on the left hand side, otherwise the place and route process is likely to move them. Press ctrl-S to save. The constraints get saved in <project>_Implmnt\sbt\constraint\<top design file>_pcf_sbt.pcf. You will then get asked to add the file to the project. Say yes.

If you’re using source control, it’s a good idea to add this file to it. I’m not so sure about all the other junk that iCEcube generates.

Now double-click ‘Run P&R’ again and the new bitmap file will be generated, using your pin constraints.

Programming an actual chip (or at least its SPI Flash ROM) needs the Diamond Programming tool, which comes as part of the Lattice Diamond software and *not* as part of iCEcube2. That’s just another couple of gigabytes to download, and another licence (free) to acquire, so it’s a pain, but it does work.

The two largest manufacturers of FPGAs are, by far, Altera and Xilinx. They control over 80% of the market share, with Lattice and others picking up the tail end. The impact of this can be seen in EE labs and alibaba; nearly every FPGA dev board, every instructional, and every bit of coursework is based on Altera or Xilinx chips.

There’s a new contender from the east. Gowin Semiconductor has released two lines of FPGAs (Google translate) in just under two years. That’s incredibly fast for a company that appears to be gearing up to take on the Altera and Xilinx monolith.

The FPGA line released last week, the GW1N family, is comprised of two devices with 1,152 and 8,640 LUTs. These FPGAs are built on a 55nm process, and are meant to compete with the low end of Altera’s and Xilinx’ offerings. This adds to Gowin’s portfolio introduced last May with the GW2A (Google translate) family, featuring devices ranging from 18,000 to 55,000 LUTs and DSP blocks. Packages will range from easily solderable QFN32 and LQFP100, to BGA packages with more pins than an eighteenth century seamstress at the royal ball.

For comparison, Xilinx’ Spartan-6 LX family begins with devices featuring 3,840 LUTs and 216kb of block RAM, with larger devices featuring 147,443 LUTs and up to 268kb of block RAM. Altera’s Cyclone IV E devices are similarly equipped, with devices ranging from 6,272 to 114,480 LUTs. Between the two device families introduced by Gowin recently, nearly the entire market of low-end FPGAs is covered, and they’re improving on the current offerings: the GW1N chips feature random access on-chip Flash memory. Neither the low-end devices from Altera nor devices from Lattice provide random-access Flash.

The toolchain for Gowin’s new FPGAs is based nearly entirely on Synopsys’ Synplify Pro, with dedicated tools from Gowin for transforming HDL into a bitstream for the chip. This deal was inked last year. As for when these devices will make it to market, Gowin is hoping to send out kits to well-qualified devs soon, and the devices may soon show up in the warehouses of distributors.

Gowin’s FPGAs, in contrast to the vast, vast majority of FPGAs, are designed and fabbed in China. This gives Gowin a unique home-field advantage in the land where everything is made. With LVDS, DSP, and other peripherals these FPGAs can handle, Gowin’s offerings open up a wide variety of options to developers and product engineers a few miles away from the Gowin plant.

The GW1N and GW2A families of FPGAs are fairly small when it comes to the world of FPGAs. This limitation is by capability though, and not number of units shipped. It’s nearly tautological that the largest market for FPGAs would be consumer goods, and Gowin is focusing on what will sell well before digging in to higher end designs. We will be seeing these chips show up in devices shortly, and with that comes a new platform to tinker around with.

If you’re looking to make your mark on the world of open source hardware and software, you could do worse than to start digging into the synthesis and bitstream of these Gowin chips. Just months ago, Lattice’s iCE40 bitstream was reverse engineered, and already there are a few boards capitalizing on a fully open source toolchain for programmable logic. With more capable FPGAs coming out of China that could be stuffed into every imaginable product, it’s a golden opportunity for hardware hackers and developers alike.

[Thanks for the tip Antti]

Digital Signal Processing Laboratory LabVIEWBased FPGA Implementation Options

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